Input data alignment circuit and semiconductor device including the same
US9183902B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2014 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Aug 15, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input data alignment circuit includes a data sampler, a frequency divider, a polarity determination block, and a data alignment block. The data sampler provides a data sequence based on data serially input according to a data strobe signal. The frequency divider generates a data alignment signal based on a divided frequency of the data strobe signal. The polarity determination block determines a polarity of the data alignment signal and provides a control signal based on the determined polarity. The data alignment block aligns the data sequence in parallel according to data alignment signal and control signal and generates output data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.