Eight transistor (8T) write assist static random access memory (SRAM) cell
US9183922B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2013 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Jan 18, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are devices, systems and/or methods relating to an eight transistor (8T) static random access memory (SRAM) cell, according to one or more embodiments. In one embodiment, an SRAM storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first NMOS switch device serially coupled to a second NMOS switch device. In this embodiment, the gate node of the first NMOS switch device is coupled to the word line, a source node of the first NMOS switch device is coupled to the cross-coupled data latch, a gate node of the second NMOS switch device is coupled to the write column select line, and a source node of the second NMOS switch device is coupled to the cross-coupled data latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.