Methods of mitigating defects for semiconductor packages
US9184067B1 · kind B1 · utility
1Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Oct 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor packages with multiple substrates can incorporate apertures or slots between devices to minimize or reduce formation of defects during a molding process. The apertures or slots can be formed adjacent a top substrate in alignment with removable regions adjacent a bottom substrate whereby the apertures or slots can facilitate outflow of materials from cavities between the substrates. The apertures or slots may subsequently be removed in conjunction with the removable regions during a singulation process thereby producing the desired semiconductor packages with improved device reliability and yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.