Electrostatic protection for stacked multi-chip integrated circuits
US9184130B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2012 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Aug 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.