Structure and method for defect passivation to reduce junction leakage for finFET device
US9184233B2 · kind B2 · utility
5Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2013 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Feb 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant. The fin-like active region further includes fluorine species.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.