Method for manufacturing a vertical semiconductor device and vertical semiconductor device
US9184281B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2013 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Feb 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Producing a vertical semiconductor device includes: providing a semiconductor wafer including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type forming a first pn-junction with the first layer, and a third semiconductor layer of the first conductivity type forming a second pn-junction with the second layer and extending to a main surface of the wafer; forming a hard mask on the main surface that includes hard mask portions spaced apart from each other by first openings; using the hard mask to etch deep trenches from the main surface into the first layer so that mesa regions covered at the main surface by respective hard mask portions are formed between adjacent trenches; filling the trenches and first openings of the hard mask; and etching the hard mask to form second openings in the hard mask at the main surface of the mesas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.