Interconnect structure and sputtering target
US9184298B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2011 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Dec 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6756
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The interconnect structure of the present invention includes at least a gate insulator layer and an oxide semiconductor layer on a substrate, wherein the oxide semiconductor layer is a layered product having a first oxide semiconductor layer containing at least one element (Z group element) selected from the group consisting of In, Ga, Zn and Sn; and a second oxide semiconductor layer containing at least one element (X group element) selected from the group consisting of In, Ga, Zn and Sn and at least one element (Y group element) selected from the group consisting of Al, Si, Ti, Hf, Ta, Ge, W and Ni, and wherein the second oxide semiconductor layer is interposed between the first oxide semiconductor layer and the gate insulator layer. The present invention makes it possible to obtain an interconnect structure having excellent switching characteristics and high stress resistance, and in particular, showing a small variation of threshold voltage before and after the stress tests, and thereby having high stability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.