Method and apparatus for preventing digital step attenuator output power peaking during attenuation state transitions
US9184731B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 2013 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Jul 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and circuit for significantly reducing positive switching transients (glitches) of digital step attenuators (DSA's) by controlling the timing of state transitions for individual attenuator stages within a DSA. Such control prevents the DSA output power from peaking during attenuation state transitions and ensures that any transient glitch during the transition results in reduced power at the DSA output. Attenuation stage timing delay can be implemented on an integrated circuit die or “chip” for monolithic implementations of a DSA by adding circuitry which ensures that any attenuation state changes result in increased attenuation rather than decreased attenuation, thereby reducing or eliminating positive transient glitches at the DSA output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.