Integrated bondline spacers for wafer level packaged circuit devices
US9187312B2 · kind B2 · utility
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3References
15Claims
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Assignee
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Key dates
| Filing date | Mar 10, 2014 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Mar 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/163
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.