Semiconductor device test structures and methods

US9188625B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Wolfgang Walter · Heidelberg, DE
• Klaus-Peter Koller · Bad Soden, DE

Key dates

• Filing date: Dec 5, 2013
• Grant date: Nov 17, 2015
• Expiry date: Dec 25, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer.