Reconfigurable memory interface circuit to support a built-in memory scan chain
US9188642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2013 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Sep 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.