Generate random numbers using metastability resolution time
US9189202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2013 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Jun 27, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/588
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is provided for a circuit for generation of a random output. A bistable circuit has two stable states as an output and a clock signal as an input. The bistable circuit includes a first logic circuit and a second logic circuit cross-coupled connected together, which transition into a metastable state before resolving to the two stable states. The second logic circuit resolves to a stable state at a resolution time. A digitization circuit is configured to generate random bits corresponding to a variance of the resolution time of the second logic circuit resolving from the metastable state to the stable state for cycles of the clock signal. The resolution time randomly varies according to noise. An actual value of the stable state is eliminated as factor in generating the random bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.