Caching agent for deadlock prevention in a processor by allowing requests that do not deplete available coherence resources
US9189296B2 · kind B2 · utility
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3References
25Claims
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Assignee
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Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Dec 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a caching agent for preventing deadlock in a processor. The caching agent includes a receiver configured to receive a request from a core of the processor. The caching agent includes ingress logic coupled to the receiver to determine that the request is potentially a cacheable request. The ingress logic is to determine that the request does not deplete an available coherence resource. The ingress logic is to allow the request to be processed in response to the determination that the request does not deplete the available coherence resource.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.