Apparatus and method for memory-mapped register caching
US9189398B2 · kind B2 · utility
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13Claims
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Key dates
| Filing date | Dec 28, 2012 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Aug 2, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is described comprising: an architectural register file implemented as a combination of a register file cache and an architectural register region within a level 1 (L1) data cache, and a data location table (DLT) to store data indicating a location of each architectural register within the register file cache and/or the architectural register region within the L1 data cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.