Patent · US Active

Interface logic for a multi-core system-on-a-chip (SoC)

US9189439B2 · kind B2 · utility

6Cited by

5References

19Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ramana Rachakonda · Austin, US
Lance Hacking · Spanish Fork, US
Mahesh K. Reddy · Austin, US
Lori R. Borger · Phoenix, US
Chee Hak Teh · Kampung Bukit Kechil, MY
Pawitter P. Bhatia · Chandler, US
John Lee · Gunpo-si, KR

Key dates

Filing date	Dec 27, 2013
Grant date	Nov 17, 2015
Priority date	—
Expiry date	Feb 12, 2034

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.