Scalable neural hardware for the noisy-OR model of Bayesian networks
US9189729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2012 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | May 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N7/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to a scalable neural hardware for the noisy-OR model of Bayesian networks. One embodiment comprises a neural core circuit including a pseudo-random number generator for generating random numbers. The neural core circuit further comprises a plurality of incoming electronic axons, a plurality of neural modules, and a plurality of electronic synapses interconnecting the axons to the neural modules. Each synapse interconnects an axon with a neural module. Each neural module receives incoming spikes from interconnected axons. Each neural module represents a noisy-OR gate. Each neural module spikes probabilistically based on at least one random number generated by the pseudo-random number generator unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.