Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations, and related systems and methods
US9190141B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2013 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Jan 19, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations are disclosed. Related systems and methods are also disclosed. To reset a plurality of SRAM bitcells in a single reset operation, a biasing circuit is provided and coupled to the plurality of SRAM bitcells. The biasing circuit is configured to apply a voltage or current bias to the SRAM bitcells during a reset operation after power provided to the SRAM bitcells is collapsed to a collapsed power level below an operational power level. The bias is applied as the power to the SRAM bitcells is restored to an operational power level, thus forcing the SRAM bitcells into a desired state. In this manner, the SRAM bitcells can be reset in a single reset operation without need for an increased drive strength from a reset circuit and without need to provide specialized SRAM bitcells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.