Lead frame and substrate semiconductor package
US9190353B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2013 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Feb 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip package includes a lead frame having a die paddle, leads surrounding the paddle and a central window through the paddle. A substrate has a base side and a superior side. A peripheral portion of the base side is secured to the paddle and a central portion of the base side is exposed through the central window. A semiconductor chip is secured to the superior side of the substrate. The semiconductor chip is electrically connected to the plurality of leads and the substrate. A mold compound covers at least portions of the lead frame, the substrate and the semiconductor chip. The chip package can be electrically connected to other devices or a circuit board by way of the leads and BGA pads of the substrate exposed in the central window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.