Three-dimensional chip-to-wafer integration
US9190391B2 · kind B2 · utility
12Cited by
9References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2011 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Feb 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.