Thermally enhanced three-dimensional integrated circuit package
US9190399B2 · kind B2 · utility
7Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2014 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Mar 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16747
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention disclose a semiconductor structure and method for increasing thermal dissipation in a three-dimensional integrated circuit package. In certain embodiments, the semiconductor structure comprises a logic die or a processor die attached to a substrate; a memory die stack attached to the logic die or the processor die; and a first lid attached to a first side of the logic or the processor die. The semiconductor structure further comprises a second lid attached to a second side of the memory die stack; a first heat sink attached to the first lid; and a second heat sink attached to the second lid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.