Digital circuit design with semi-continuous diffusion standard cell
US9190405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2014 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Jan 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/931
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CMOS device including a standard cell includes first and second transistors with a gate between the first and second transistors. One active region extends between the first and second transistors and under the gate. In a first configuration, when drains/sources of the first and second transistors on the sides of the gate carry the same signal, the drains/sources are connected together and to the gate. In a second configuration, when a source of the first transistor on a side of the gate is connected to a source voltage and a drain/source of the second transistor on the other side of the gate carries a signal, the source of the first transistor is connected to the gate. In a third configuration, when sources of the first and second transistors on the sides of the gate are connected to a source voltage, the gate floats.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.