Method with system and program product for prioritizing clock domains for testing of integrated circuit designs

US9194916B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Douglas E. Sprague · Jericho, US
• Philip Stevens · Stuttgart, DE

Key dates

• Filing date: Jan 2, 2014
• Grant date: Nov 24, 2015
• Expiry date: Mar 16, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/396
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

The present disclosure generally provides for a method of prioritizing clock domains for testing an integrated circuit (IC) design. The method can include: assigning each of a plurality of multi-tested clock domains (MTCDs) and a plurality of test experiments (TEs) to one of a plurality of speed priority groups (SPGs), wherein the assigning includes: creating a new SPG having a priority value of n+1, wherein n represents the number of previously created SPGs; assigning a first MTCD corresponding to at least two of the plurality of TEs, the first MTCD not being previously assigned to an SPG, to the new SPG; and assigning each TE corresponding to the first MTCD, each of the assigned TEs not being previously assigned to an SPG, to the new SPG; and performing each of the plurality of TEs on the IC design in order from lowest priority value to highest priority value.