Synchronizing data from different clock domains by bridges one of the clock signals to appear to run an integer of cycles more than the other clock signal
US9195261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2013 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Aug 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus may include: first circuitry configured to operate at a first frequency; second circuitry configured to operate at a second frequency that is different from the first frequency, where the second circuitry is for receiving input from, and for providing output to, the first circuitry; and logic that bridges the first circuitry and the second circuitry. The logic to enables the second circuitry to appear to run an integer number of cycles of the first frequency, and operates by receiving first signals at the first frequency and generating second signals at the second frequency, where the second signals are for triggering operations performed by the second circuitry. The apparatus may also include an output buffer circuit bridging the first circuitry and the second circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.