Patent · US Active

Cache coherency and processor consistency

US9195465B2 · kind B2 · utility

0Cited by

1References

18Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Varun K. Mohandru · Braunschweig, DE
Fernando Latorre · Soria, ES
Li-Gao Zei · Braunschweig, DE
Allan D. Knies · San Francisco, US
Rami May · Haifa, IL
Lutz Naethke · Braunschweig, DE

Key dates

Filing date	Dec 28, 2012
Grant date	Nov 24, 2015
Priority date	—
Expiry date	May 9, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/507
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Responsive to execution of a computer instruction in a current translation window, state indicators associated with a cache line accessed for the execution may be modified. The state indicators may include: a first indicator to indicate whether the computer instruction is a load instruction moved from a subsequent translation window into the current translation window, a second indicator to indicate whether the cache line is modified in a cache responsive to the execution of the computer instruction, a third indicator to indicate whether the cache line is speculatively modified in the cache responsive to the execution of the computer instruction, a fourth indicator to indicate whether the cache line is speculatively loaded by the computer instruction, a fifth indicator to indicate whether a core executing the computer instruction exclusively owns the cache line, and a sixth indicator to indicate whether the cache line is invalid.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.