Multi-level aggregation techniques for memory hierarchies
US9195599B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2013 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Jan 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments include method, system, and computer program product for providing aggregation hierarchy that is related memory hierarchies. In one embodiment, the method includes determining capacity of a first level memory of a memory hierarchy for processing data relating to completion of an aggregation process and generating a per thread local look-up table in said first level memory upon determining said capacity. Upon the first level memory reaching capacity, a plurality of per thread partitions to store remaining data to complete the aggregation process in a second level memory of the memory hierarchy is generated such that each of said per-thread partitions includes an identical amount of data portion on each thread. The method also includes storing the per thread partitions in said second level memory and providing a single global look up table for each of the identical data portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.