Dynamic memory cache size adjustment in a memory device
US9195604B2 · kind B2 · utility
7Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Oct 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.