Patent · US Active

Common shared memory in a verification system

US9195784B2 · kind B2 · utility

17Cited by

58References

50Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Ping-Sheng Tseng · Saratoga, US
Sharon Sheau-Pyng Lin · Cupertino, US
Quincy Kun-Hsu Shen · Union City, US
Mike Mon Yen Tsai · Los Altos Hills, US
Steven Wang · Cupertino, US

Key dates

Filing date	Apr 1, 2011
Grant date	Nov 24, 2015
Priority date	—
Expiry date	Apr 1, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.