Incremental functional verification of a circuit design
US9195789B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Jul 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and a method are disclosed for verifying the implementation of a computer chip design. A design including one or more interpretive computer programing language modules and one or more hardware description language (HDL) modules is received. When one of the interpretive programing language modules requests to communicate with one of the HDL modules, the HDL module is enabled and the input arguments from the interpretive programing language module are pipelined into the HDL module. Pipelined output data is received from the HDL module. The received output data is formatted and returned to the interpretive programing language module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.