On-die termination apparatuses and methods
US9196321B2 · kind B2 · utility
8Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2013 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Dec 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.