Resistance-based memory cells with multiple source lines
US9196339B2 · kind B2 · utility
1Cited by
2References
25Claims
0Family size
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Key dates
| Filing date | Sep 30, 2013 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Jan 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a particular embodiment, a device includes a resistance-based memory cell having multiple source lines and multiple access transistors. A coupling configuration of the multiple access transistors to multiple source lines encodes a data value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.