Device including a plurality of memory banks and a pipeline control circuit configured to execute a command on the plurality of memory banks
US9196351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Feb 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for carrying out read and write operations in a synchronous memory device having a shared I/O, includes receiving a read command directed to a first internal memory bank during a first timeslot, activating the first internal memory bank to access read data at a read address requested by the read command, receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot, determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur, and receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.