Dual shallow trench isolation and related applications
US9196547B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2010 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Apr 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to dual shallow trench isolations (STI). In various embodiments related to CMOS Image Sensor (CIS) technologies, the dual STI refers to one STI structure in the pixel region and another STI structure in the periphery or logic region. The depth of each STI structure depends on the need and/or isolation tolerance of devices in each region. In an embodiment, the pixel region uses NMOS devices and the STI in this region is shallower than that of in the periphery region that includes both NMOS and PMOS device having different P- and N-wells and that desire more protective isolation (i.e., deeper STI). Depending on implementations, different numbers of masks (e.g., two, three) are used to generate the dual STI, and are disclosed in various method embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.