Perforated electronic package and method of fabrication
US9196590B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Mar 6, 2015 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Mar 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package includes an integrated circuit chip mounted to a support plate and encapsulated by an encapsulating body. The package includes at least one weakening deep perforation. The perforation is formed in either the support plate or the encapsulating body, and functions to reduce a resistance of the package to bending stresses perpendicular to the support plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.