Semiconductor device having metal bit line
US9196619B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Jun 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
Disclosed herein is a device that includes: a semiconductor substrate including a memory cell region and a peripheral circuit region arranged around the memory cell region; an element isolation region formed in the memory cell region and the peripheral circuit region; a cell active region defined by the element isolation region formed in the memory cell region; a first interlayer insulation film disposed on the cell active region, the first interlayer insulation film having a bit contact hole passing therethrough to expose a portion of an upper surface of the cell active region; and a bit line having a first metal laminated film, the bit line being disposed on the first interlayer insulation film so as to fill the bit contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.