Semiconductor devices having carbon-contained porous insulation over gate stack structures
US9196630B2 · kind B2 · utility
4Cited by
2References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Oct 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.