Method of fabricating a vertical MOS transistor
US9196654B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 8, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Jan 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/122
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.