Tensile nitride profile shaper etch to provide void free gapfill
US9196684B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Apr 16, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Apr 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method of reducing the impact of FEoL topography on dual stress liner depositions and the resulting device are disclosed. Embodiments include forming a first nitride layer between and over a pFET and an nFET; thinning the first nitride layer; forming a second nitride layer over the first nitride layer; and removing the first and the second nitride layers from over the pFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.