Selective laser annealing process for buried regions in a MOS device
US9196704B2 · kind B2 · utility
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2References
15Claims
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Key dates
| Filing date | Dec 19, 2011 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Jan 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Laser anneal to melt regions of a microelectronic device buried under overlying materials, such as an interlayer dielectric (ILD). Melting temperature differentiation is employed to selectively melt a buried region. In embodiments a buried region is at least one of a gate electrode and a source/drain region. Laser anneal may be performed after contact formation with contact metal coupling energy into the buried layer for the anneal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.