Backside bulk silicon MEMS
US9196752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2011 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Feb 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An integrated circuit device that comprises a single semiconductor substrate, a device layer formed on a frontside of the single semiconductor substrate, a redistribution layer formed on a backside of the single semiconductor substrate, a through silicon via (TSV) formed within the single semiconductor substrate that is electrically coupled to the device layer and to the redistribution layer, a logic-memory interface (LMI) formed on a backside of the single semiconductor substrate that is electrically coupled to the redistribution layer, and a MEMS device formed on the backside of the single semiconductor substrate that is electrically coupled to the redistribution layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.