Apparatus and method for correcting output signal of FPGA-based memory test device
US9197212B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Jul 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for correcting an output signal of an FPGA-based memory test device includes a clock generator for outputting clock signals having different phases; and a pattern generator for outputting an address signal, a data signal and a clock signal in response to the clock signals input from the clock generator, and correcting a timing of each of the output signals using flip flops for timing measurement. Wherein the address signal, the data signal and the clock signal, through a pattern generator, are implemented with a programmable logic such as FPGA, thereby shortening the correcting time without the use of an external delay device, and increasing accuracy of output timing of the signal for memory testing, ultimately enhancing performance (accuracy) of a memory tester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.