Floating point matrix multiplication co-processor
US9201848B2 · kind B2 · utility
0Cited by
2References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 12, 2012 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Jun 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Invention providing a means for performing matrix multiplication that may be implemented in hardware or software. The invention is scalable to matrices of varying dimension and to permit balancing circuit complexity versus processing throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.