Write word-line assist circuitry for a byte-writeable memory
US9202555B2 · kind B2 · utility
16Cited by
7References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 19, 2012 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Sep 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write-assisted memory. The write-assisted memory includes a word-line decoder that is implemented within a low VDD power domain. The write-assisted memory also includes a write-segment controller that is partially implemented within the low VDD power domain and is partially implemented within a high VDD power domain. The write-assisted memory further includes a local write word-line decoder that is implemented within the high VDD power domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.