Three-dimensional two-port bit cell
US9202557B2 · kind B2 · utility
8Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2013 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Feb 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes a read port array disposed on a first layer of a three-dimensional integrated circuit and a bit cell array disposed on a second layer of the three-dimensional integrated circuit. The second layer being vertically positioned above or below the first layer. At least one bit cell of the bit cell array is coupled to at least one read port cell of the read port array by a via extending from the first layer to the second layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.