Flash-memory low-speed read mode control circuit
US9202582B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2014 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Dec 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a flash-memory low-speed read mode control circuit, which comprises a charge pump, a first voltage division circuit composed of two resistors and a first switch interconnected in series, and a second voltage division circuit composed of two capacitors interconnected in series. The first switch is used for switching between the data read mode of the low-speed read mode and the charge pump electric-leakage mode. In the data read mode, a first component voltage formed by the two resistors is fed back to the input terminal of the charge pump through a comparator, an NAND gate and a buffer, making a stable value of the output voltage of the charge pump proportional to the first component voltage. In the charge pump electric-leakage mode, the second voltage division circuit monitors the output voltage of the charge pump: when the output voltage is below a low threshold voltage, a feedback signal is formed and sent to the input terminal of the charge pump to make the charge pump turned on; when the output voltage is above a low threshold voltage, a feedback signal is formed and sent to the input terminal of the charge pump to make the charge pump stop worki…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.