Capping dielectric structure for transistor gates
US9202699B2 · kind B2 · utility
8Cited by
8References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2011 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Jun 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present description relates to the field of fabricating microelectronic transistors, including non-planar transistors, for microelectronic devices. Embodiments of the present description relate to the formation a recessed gate electrode capped by a substantially void-free dielectric capping dielectric structure which may be formed with a high density plasma process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.