Inventor · Campbell, CA, US

Sameer Pradhan

29Patents
6h-index
26Co-inventors
65Inventor score

Filing activity: Mar 3, 2006 → May 18, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US7751654B2 Electro-optic modulation Physics 58 Active
US9299801B1 Method for fabricating a transistor device with a tuned dopant profile Electricity 14 Active
US9112057B1 Semiconductor devices with dopant migration suppression and method of fabrication thereof Electricity 10 Active
US9202699B2 Capping dielectric structure for transistor gates Electricity 8 Active
US9177867B2 Tungsten gates for non-planar transistors Electricity 7 Active
US9196727B2 High uniformity screen and epitaxial layers for CMOS devices Electricity 6 Active
US8981435B2 Source/drain contacts for non-planar transistors Electricity 6 Active
US8877619B1 Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom Electricity 6 Active
US9041126B2 Deeply depleted MOS transistors having a screening layer and methods thereof Electricity 4 Active
US9425316B2 Source/drain contacts for non-planar transistors Electricity 3 Active
US8637955B1 Semiconductor structure with reduced junction leakage and method of fabrication thereof Electricity 3 Active
US9853156B2 Source/drain contacts for non-planar transistors Electricity 2 Active
US9577041B2 Method for fabricating a transistor device with a tuned dopant profile Electricity 2 Active
US8883600B1 Transistor having reduced junction leakage and methods of forming thereof Electricity 2 Active
US9368624B2 Method for fabricating a transistor with reduced junction leakage current Electricity 2 Active
US9087915B2 Interlayer dielectric for non-planar transistors Electricity 1 Active
US10056488B2 Interlayer dielectric for non-planar transistors Electricity 1 Active
US9580776B2 Tungsten gates for non-planar transistors Electricity 0 Active
US10020375B2 Tungsten gates for non-planar transistors Electricity 0 Active
US9812546B2 Tungsten gates for non-planar transistors Electricity 0 Active
US9105711B2 Semiconductor structure with reduced junction leakage and method of fabrication thereof Electricity 0 Active
US9634124B2 Interlayer dielectric for non-planar transistors Electricity 0 Active
US10693006B2 Interlayer dielectric for non-planar transistors Electricity 0 Active
US9893148B2 Method for fabricating a transistor device with a tuned dopant profile Electricity 0 Active
US10998445B2 Interlayer dielectric for non-planar transistors Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.