Hybrid integrated semiconductor tri-gate and split dual-gate FinFET devices and method for manufacturing

US9202762B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Deyuan Xiao · Shanghai, CN
• Guo Qing Chen · Boise, US
• Roger Lee · Boise, US

Key dates

• Filing date: Jan 6, 2011
• Grant date: Dec 1, 2015
• Expiry date: Oct 5, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6215

Abstract

A method for making an integrated circuit includes at least a tri-gate FinFET and a dual-gate FinFET. The method includes providing a semiconductor on insulator (SOI) substrate. The method also includes implanting impurities into the substrate for adjusting a threshold voltage. The method provides a nitride film overlying a surface region of the substrate and selectively etches the silicon nitride film to form a nitride cap region. The method etches the silicon layer to form a first and a second silicon fin regions. The nitride cap region is maintained on a portion of a surface region of the first silicon fin region. The method includes forming a gate dielectric, depositing a polysilicon film, and planarizing the polysilicon film by chemical mechanical polishing (CMP) using the nitride cap region as a polish stop. The method etches the polysilicon film to form gate electrodes. The method forms elevated source and drain regions.