Defect pattern evaluation method, defect pattern evaluation apparatus, and recording media
US9202763B2 · kind B2 · utility
1Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Jul 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/2817
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to a defect pattern evaluation method of an embodiment, defects are detected by performing optical defect inspection on a pattern on a substrate. Then, the defects are classified according to a type of a pattern layout using a pattern layout corresponding to coordinates of the defects. Further, a computer calculates a defect occurrence rate by dividing the number of defects of each pattern layout by an arrangement number of the pattern layouts in an inspection region. Then, the defect occurrence rate of each pattern layout is output as an evaluation result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.