Circuitry and method for correcting 3-bit errors containing adjacent 2-bit error

US9203437B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thomas Kern · Munich, DE
• Ulrich Backhausen · Taufkirchen, DE
• Thomas Rabenalt · Unterhaching, DE
• Christian Badack · Heinsberg, DE
• Michael Goessel · Roter Dudel, DE

Key dates

• Filing date: Dec 19, 2012
• Grant date: Dec 1, 2015
• Expiry date: Dec 11, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03M13/616
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A circuitry is proposed for the correction of errors in a possibly erroneous binary word v′=v′1, . . . , v′n relative to a codeword v=v1, . . . , vn, in particular 3-bit errors containing an adjacent 2-bit error (burst error). The circuitry comprises a syndrome generator and a decoder. A modified BCH is used wherein n′ column vectors of a first BCH code submatrix are paired as column vector pairs so that a componentwise XOR combination of the two column vectors of each column vector pair produces an identical column vector K that is different from all column vectors of the first BCH submatrix. A second BCH submatrix comprises corresponding column vectors as the third power, according to Galois field arithmetic, of the column vector in the first BCH submatrix. The syndrome generated by the syndrome generator can be checked against the columns of the first and second submatrices.