Functional screening of static random access memories using an array bias voltage
US9208832B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2012 |
| Grant date | Dec 8, 2015 |
| Priority date | — |
| Expiry date | May 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.